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A 512-mb DDR3 SDRAM prototype with C/sub IO/ minimization and self-calibration techniques | IEEE Journals & Magazine | IEEE Xplore

A 512-mb DDR3 SDRAM prototype with C/sub IO/ minimization and self-calibration techniques


Abstract:

A 1.5-V 512-Mb DDR3 synchronous DRAM prototype was designed and fabricated in 80-nm technology. Critical to the signal integrity in DDR3 point-to-2points (P22P) interfaci...Show More

Abstract:

A 1.5-V 512-Mb DDR3 synchronous DRAM prototype was designed and fabricated in 80-nm technology. Critical to the signal integrity in DDR3 point-to-2points (P22P) interfacing is an efficient calibration scheme and C/sub IO/ minimization, which were achieved by on-die-termination (ODT)-merged output drivers, SCR type ESD protection, and self-calibration scheme. The hybrid latency control scheme can turn the DLL off in standby mode, reducing power consumption. User-friendly functions such as temperature read-out from on-chip sensor and per-bank-refresh were also implemented.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 41, Issue: 4, April 2006)
Page(s): 831 - 838
Date of Publication: 30 April 2006

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