Structured low-density parity-check code design for next generation digital video broadcast

We describe a novel design for low-density parity-check (LDPC) codes that eliminates the routing problem associated with LDPC decoder implementation resulting in a small silicon area in application specific integrated circuits (ASICs). Unlike previous solutions that require a large number of small and hence area inefficient memory blocks, this design allows collision-free memory access on a single memory block by imposing certain restrictions on the parity check matrix of the codes. Therefore, it leads to substantially smaller circuits. Furthermore the resulting codes have outstanding error rate performance very close to Shannon limit for a wide range of throughputs from 0.5 bits/symbol up to 4 bits/symbol. As a result LDPC codes designed with this method have been standardized for the next generation digital video broadcasting (DVB).