Design of CMOS quadrature modulator for WLAN 802.11a application

This paper describes the design of a 1-GHz quadrature modulator for 802.11a WLAN systems with TSMC 0.18-/spl mu/m CMOS technology. By using an improved double-balanced mixer combined with a double-balanced mixer, a common-mode feedback circuit and an improved transconductance amplifier, the linearity of the modulator is improved. The experimental results show the modulator achieves -5 dBm for P/sub 1 dB/, -42 dB for LO-IF isolation, and a gain of 1.2 dB. The power consumption is 49 mW with a 1.8-V power supply.