A low noise 0.9GHz FBAR clock

A low noise 0.9GHz FBAR clock consisting of an oscillator and divider circuit for single sided-to-differential conversion for high-speed A/D-converter was designed, realized with an in-house FBAR and a commercial 0.35 /spl mu/m CMOS process, and tested. The circuit showed very good jitter and phase noise performance.