Power-performance analysis of sinusoidally clocked flip-flops

This paper can be viewed as a supplement to recent interest in different on-chip resonant clocking techniques. We present a study on the impact of sinusoidal clock signals on power and performance of six conventional flip-flops. The dominating effects are delay penalties of 20-30 % for the best flip-flops, and reduced race-margins. Two-phase master-slave flip-flops and single-phase sense-amplifier flip-flops both obtain robust timing behavior, and minimum power-delay degradation.