Architecture of an embedded queue management engine for high-speed network devices

Network buffers used in network devices, have to allow line-speed buffering of packets while they maintain a large number of queues. Due to the growing speed of network links and the increasing number of data queues, the design of network embedded systems operating at high speeds is often restricted by their memory subsystem performance. In this paper, we show architecture of a network buffer subsystem which efficiently manages storing and retrieving data packets of multi gigabit network lines among 16 K different queues. The proposed architecture is implemented in FPGA and uses available memory technologies. It is ideal to be used as a queue management component in network processors, switches, stream processors, or any other application which require high-performance queue management engines