A low power decomposed hierarchical multiplier architecture embedding multiplexer based full adders

This paper proposes a novel 4/spl times/4 multiplier architecture which is efficient in terms of power without a significant increase in delay and area, especially designed for partition multipliers having a partition size of 4. The idea involves the generation of partial products in parallel using AND gates. The addition of these partial products will take log2 (2N), which in this case would take 3 steps since, the operand width N is 4. In the proposed multiplier, computation is divided into hierarchical levels saving significant amount of power, since, power is provided only to the level that is involved in computation and thereby rendering the remaining two levels inactive. In order to further reduce the power consumption, the proposed 4/spl times/4 multiplier architecture uses the recently proposed low-power multiplexer-based 1-bit full adder. To further improve on the power efficiency, novel 6 transistors half adder architecture is proposed. Furthermore, a low power AND gate is also designed for generation of partial products.