Application-specific PLD targeting super semi-systolic designs

This paper proposes a new PLD architecture targeting a super semi-systolic array - a derivative from a super-systolic array - for application-specific arithmetic operations such as MAC. This architecture combines the high performance of ASICs with the flexibility of PLDs and it offers a significant alternative view on the programmable logic devices. The super semi-systolic array is ideal for a newly proposed PLD architecture in terms of area-efficiency, P&R and clock speed