A 1 V 0.8mW multi-GHz CMOS differential tunable image reject notch filter

This paper presents a new implementation of a CMOS differential image reject filter at 8 GHz, combined with a folded-cascode 5.8 GHz low-noise amplifier, aiming at implementing fully integrated heterodyne receiver frontends. The filter consumes 0.8 mW from a 1 V supply, while providing 58 dB of image rejection in a standard CMOS 0.18 /spl mu/m technology. Q-enhancement circuitry for on chip inductors are used to optimize the depth of image rejection.