Behavioral modeling of /spl Sigma//spl Delta/ modulators using VHDL-AMS

Sigma delta modulators (SigmaDeltaMs) form part of the core of today's mixed-signal designs as the cornerstone elements of oversampled analog-to-digital (A/D) and digital-to-analog (D/A) converters. Although transistor-level simulation is the most accurate approach known for these components, this method becomes impractical for complex systems due to the long computational time required. Behavioral modeling is a viable solution to the extensive simulation time of SigmaDeltaMs. This work presents a VHDL-AMS behavioral model of a discrete-time (DT) second-order multibit SigmaDeltaM. Preliminary results from the VHDL-AMS model quantifying the signal-to-noise plus distortion ratio (SNDR) in a bandwidth of 200KHz indicate an error of only 0.65% with respect to experimental data used in the validation of the previous model. Work in progress seeks to validate the switched-capacitor (SC) integrator model in the WCDMA compatible bandwidth at 2.0MHz. At these frequencies, our preliminary analyses indicate errors increasing up to 7.7%. Further analyses are under way to reduce these errors, particularly through refinement of noise models and the sources of nonidealities in the SC network