Reducing power and delay in memory cells using virtual source transistors

Seven novel static RAM cells are described in this paper. All seven are a variation of the six-transistor differential memory cell containing a two-inverter feedback loop with n-type pass transistors between the inverter inputs and the bit-lines. Each variation contains some combination of virtual source transistors (virtual ground or V/sub DD/) and transmission gates. Power and delay values are given for each of the seven designs with minimum sized transistors, as well as a discussion of improved performance with wider pass transistors. The new cells with the best performance in the areas of power consumption, delay, and power-delay product demonstrate improvements of 27.6%, 12.2%, and 24.1% respectively.