Tri-State based Shifters in FPGA: Comparison and Optimization

This paper discusses the technique of implementing shifters on FPGA using tri-state buffers and provides a comparison against the standard technique of implementing shifters using combinational logic. The overview of utilized resources, power and speed is also provided. Further more enhancements which can be made to tri-state buffer based shifters by optimizing the control circuitry and hence making the new technique viable in terms of area, speed and power are also discussed.