FPGA Based Implementation of MPEG-2 Compression Algorithm

This paper presents the hardware implementation of MPEG-2 compression algorithm on FPGA. Different sections including Discrete Cosine Transform (DCT), Quantization, Motion Estimation and Compensation of MPEG-2 algorithm were implemented and it was concluded from the results that the technique used provides best solution in terms of Peak Noise to Signal Ratio (PNSR) and computational complexity to reduce the Sum of Absolute Difference (SAD) operations for the motion estimation. Hierarchical based motion estimation technique was used to reduce the SAD computations. Spartan3 FPGA based technology was used in research. Comparison was performed before and after the compression, results were analyzed and the experimental results showed that the proposed architecture had the high computational efficiency and PNSR results.