A vertically integrated GaAs bipolar DRAM cell

Bipolar DRAM cells consisting of an n-p-n homojunction bipolar transistor integrated vertically over a p-n junction storage capacitor was fabricated and characterized. The floating collector of the access transistor was merged with the n-region of the storage capacitor. The n-type emitter was connected to the bit line and the p-type base was connected to the word line; the p-type substrate served as the ground plate of the storage capacitor. Storage times of up to 8 min were observed in these cells at room temperature. With a half-bandgap activation energy, these cells should have adequate (>100 ms) storage times up to 125 degrees C. Electrical writing was confirmed by monitoring the capacitance of the storage capacitor while write pulses were applied to the word line.