Enhancement of lithographic patterns by using serif features

Serifs were designed for the thin-oxide level pattern of a CMOS SRAM cell with submicrometer design rules, using two-dimensional aerial image simulations for optimization. Results of experiments using I-line lithography showed good agreement with the simulations, and significant pattern shape improvement was observed when serifs were used. The proximity effects in the electron-beam mask-making process were found to reduce the full effectiveness of this technique due to the resulting deviations in serif sizes on the reticle. Further enhancement of pattern fidelity may be possible if this issue is resolved.<>