VLSI Test Expertise System Using a Control Flow Model

The automatic generation of test programs for VLSI circuits and systems remains an unanswered wish. The solution seems to be a computerized expert aid, integrated in a whole system for circuit design. This paper outlines the concepts of an intelligent agent whose aims are to help the designer in appraising the diagnosability of the device or the system under design, to suggest design modifications, to generate test patterns for elementary modules and to assemble the basic test sequences into a test program for the whole circuit. Emphasis is put in this paper on this last task, especially for systems described by a control flow model (CADOC langage) which is suitable for VLSI circuits like general purpose or dedicated microprocessors, distributed controllers, etc... The CAT system works like an intelligent assistant for test program generation and like an expert system for the diagnosis on the chip.