A Layout Synthesis System for NMOS Gate-Cells

A synthesis system for the automatic layout of NMOS gate cells is described. The cells are based on multigrid cell models and are intended for use as part of a chip synthesis system. An outline of the basic concepts of a CAD procedure for the layout synthesis of such cells is given. The main objective is to generate correct and compact cells with controlled growth in area when subjected to modified speed requirements. Both the layout synthesis procedure itself and algorithms are discussed.