A random access scans architecture to reduce hardware overhead

In this paper we propose architecture for random access scan (RAS) that minimizes the signals to the RAS flip-flops (FF), and provide an estimate of the area overhead. Two global signals, scan-in and mode control, have been eliminated compared to previous RAS designs presented in the literature. For 'n' flip-flops, instead of routing 'n' address wires, one to each FF, we use /spl radic/n wires in an 'x-y' matrix layout. A unique toggle mechanism is introduced in the RAS FF that eliminates the scan-in signal wire and reduces the vector set up time to 60% compared to traditional serial scan (SS). Serial scan induces unnecessary circuit activity during scan that causes the circuit under test (CUT) to dissipate a significant amount of power. Our design reduces this power dissipation by 99%. The problem of delay testing is highly constrained in SS and the scan-cell is often modified to assist delay testing. Any single input change delay test can be directly applied in our design. Hence all testable paths in the circuit can be effectively tested without constraints. We also propose a multistage scan-out system to observe the addressed FF avoiding a slow output bus.