Exceptional ASIC: through automatic timing exception generation (ATEG)

The next inclusion in the industrial ASIC design flow is going to be automatic timing exception generation (ATEG). The current manual and reactive approach of identifying timing exceptions and doing timing closure through iterations were addressed. With ATEG tools able to make the design more transparent, the major advantage will be seen on the implementation of complex SoC designs with dozens of third party IP cores with very limited design knowledge on these IP. Add to this automatic constraints generation (ACG) tool, capable of doing automatic clock definition and constraints generation, the design flow matures to an ideal design flow. The paper went through in detail of an experiment for evolving a new design flow for optimal usage of ATEG for better timing closure and quality of result (QoR) with less number of iterations. It first covered the problems faced during inclusion of ATEG in the existing design flow and how they are solved in the new design flow. The design flow shall be robust to accept any ATEG tool and get the maximum advantage. The paper shared the details of an actual design implementation in the ATEG flow and the results compared with that of the existing standard design flow. It ended with suggestions for making a simple and flexible ATEG flow for targeted design implementation goals and also a wish list for upcoming ATEG tools.