CMOS class-AB voltage-mode multiplier

A novel circuit configuration for a CMOS voltage-mode four-quadrant analog multiplier is described. It is based on square law characteristic of MOS transistor and class-AB amplifier. The multiplier achieves a linearity of 1.1%, -3 dB bandwidth of 35 MHz, and a total harmonic distortion of 0.76%. The power consumption is 1.5 mW.