Single low-supply and low-distortion CMOS analog multiplier

A single low-supply CMOS analog multiplier based upon ohmic region of MOS transistors is presented. This paper describes a method to force the drain-source voltage (V/sub DS/) of MOS transistors to operate in ohmic region. The achieved circuit can be used a single low-power supply. The complete circuit contains 20 transistors and 8 current sources using a low-power supply +1.5 volts. This circuit has high performance with very high-linearity and low-distortion. The achieved input dynamic range operation is /spl plusmn/400 mV, the linearity error is smaller than 0.1% and total harmonic distortion is smaller than 0.25% for input range 800 mVp-p.