Lateral integration of partially insulated and bulk MOSFETs using partial SOI process

We proposed and successfully demonstrated partially insulated and bulk MOSFETs with multiple V/sub th/s, I/sub on/s, and I/sub Off/s by using partial SOI process without complex process and SOI wafer. Both nMOS and pMOS applicable to the HP and LSTP transistors were simultaneously implemented on the same wafer with the same process except partial SOI process. These results must be very useful to implement IC systems requiring various specifications of V/sub TH/s, I/sub On/s, and I/sub Off/s.