A 2.4-GHz Bluetooth CMOS transceiver for wireless LANs

In this paper, a design of a 2.4-GHz Bluetooth transceiver for wireless LANs is presented. The receiver design uses a heterodyne architecture with a single stage analog down-conversion to the intermediate frequency. The signal at the intermediate frequency is directly digitized to allow filtering and demodulation to be done digitally. The major advantage of the design is that while high IF is used to improve image rejection the sampling frequency can be much lower than IF instead of four times the IF that is used in the traditional designs. Lowering the sampling frequency reduces the power consumption of the modulator and subsequent digital signal processing stage which is one of the key features of the Bluetooth standard. Moreover, lowering the sampling rate allows using standard CMOS technology for the fabrication of the transceiver. In addition to analog to digital conversion, the digitizer architecture down-converts the IF signal to a digital frequency that is much lower than IF. The design uses a low-noise amplifier with LC tank circuit with Q enhancement technique which provide amplification as well as filtering and eliminates the need to the off-chip RF SAW filter that is normally used. Moreover, using Q-enhancement technique allows using on-chip inductors resulting in a design that can be fully integrated. The targeted technology is a 0.35-nm standard CMOS with an operating voltage of 3 volts.