CMOS high-resolution all-digital phase-locked loop

The core of an all-digital phase locked-loop (ADPLL) is composed of a high resolution digital controlled oscillator (DCO) circuit operating in a wide frequency range, a phase-frequency detector (PFD) and an up/down binary counter. The ADPLL can be reused in many system-on-chip (SoC) applications by a proper setting of the DCO and the PFD. Extensive simulation were carried on using models of a standard 0.18/spl mu/m CMOS technology, with a power supply of 1.8 volts. The simulation results show that the ADPLL can operate from 26MHz to 588MHz.