Abstract:
Formal property verification is increasingly being adopted by designers for module level validation. The behavior of a module is typically expressed in terms of the behav...Show MoreMetadata
Abstract:
Formal property verification is increasingly being adopted by designers for module level validation. The behavior of a module is typically expressed in terms of the behavioral guarantee of the module under assumptions on its environment. Expressing such assume-guarantee properties correctly in a formal language is a nontrivial task and errors in the specification are not uncommon. In this paper we examine the main forms of specification errors for open systems, and present SAT based algorithms for verifying the specification against such errors.
Date of Conference: 06-10 November 2005
Date Added to IEEE Xplore: 19 December 2005
Print ISBN:0-7803-9254-X