Single-chip FPGA implementation of a pipelined, memory-based AES Rijndael encryption design

In this paper, we present a fully synchronous, memory-based, single-chip FPGA implementation of the recent AES standard, Rijndael encryption algorithm. Our RTL design encrypts the necessary AES rounds in an arithmetic pipeline structure. The dual-width encryption datapath uses lookup table (LUT) architecture to perform encryption with internally generated round keys. Rijndael state matrix cell entries are transformed individually at the byte-level for encryption operations such as cipher key addition, byte substitution, and shift row. Whereas, a 32-bit DSP core, inserted in the pipeline, allows for Galios field(8) arithmetic operations at the word-level of the state matrix column. Design functionality was verified using self-checking testbench with the NIST Known Answer Tests. Our FPGA implementation targets a Xilinx VirtexIIPro device. Experimental clock frequencies, throughput translations, latency-area issues and FPGA resource utilizations are presented for the memory-based design. Finally, we present a brief comparison of our FPGA implementation with other implementations of the Rijndael encryption algorithm