STE based verification of the look-aside interface

In this paper we investigate the model checking of the look-aside interface (LA-1 standard) using STE, a model checking technique based on a form of quaternary symbolic simulation. The look aside interface is intended for devices located adjacent to a network processing device (NPE) that off load certain tasks from the network processor. For our verification purpose, we first extracted some safety properties of the LA-1 interface based on its design specification. Then, we developed a synthesizable RTL model of the LA-1 interface using Verilog, which was then translated to Exlif format in order to be accepted by the STE tool. Afterwards, we described those safety properties as STE assertions and performed the verification. Finally, to evaluate our approach, we verified the same properties using the RuleBase model checker from IBM.