Substrate bias effects in vertical SiGe HBTs fabricated on CMOS-compatible thin film SOI

A comprehensive investigation of substrate bias effects on device performance, thermal properties, and reliability of vertical SiGe HBTs fabricated on CMOS-compatible, thin-film SOI, is presented for the first time. Calibrated 2D MEDICI simulations are used to support our explanations, and the resultant device design trade-offs encountered in building SiGe HBTs on thin-film SOI are quantitatively assessed.