An improved implementation method of AHB BusMatrix

The multi-layer AHB BusMatrix (ML-AHB BusMatrix) proposed by ARM allows parallel access paths between multiple masters and slaves in a system. But, there is one clock cycle delay for each master in the ML-AHB BusMatrix of ADK (AMBA/spl trade/ design kit) whenever the master restarts the transactions or changes the slave layers because of the input stage and arbitration logic implemented with Moore type. In this paper, we present one way to improve the ML-AHB BusMatrix structure of ADK. With the elimination of the input stage and some restrictions on the arbitration scheme, we could not only take away the one clock cycle delay but also reduce the area overhead and power consumption. Experimental results show that the one clock cycle delay is removed. Besides the average dynamic power, static power, total area overhead and clock period of ameliorated ML-AHB BusMatrix are reduced by 42%, 64%, 33% and 33% respectively, compared with the ML-AHB BusMatrix of ADK.