Effects of buffer layer thickness and doping concentration on SiC MESFET characteristics

Two-dimensional simulations have been carried out using the Atlas/spl reg/ device simulator to investigate the effects of the buffer layer thickness and doping concentration on the electrical characteristics of the SiC MESFET. The variations of transconductance, output resistance, gate-source capacitance, gate-drain capacitance and (cutoff frequency) f/sub T/ with respect to the change in buffer layer thickness and doping concentration have been investigated. It is observed that the performances of MESFET can be improved by reducing the leakage of channel carrier into the substrate at high drain bias, which is achieved by increasing buffer layer doping density and/or increasing buffer layer thickness. For a SiC MESFET with buffer layer thickness of 0.3/spl mu/m and gate length of 1/spl mu/m, drain current increases from 0.1 A//spl mu/m to above 0.45A//spl mu/m as the buffer layer doping density is decreased from 1.9/spl times/10/sup 17/ cm/sup -3/ to 1/spl times/10/sup 16/ cm/sup -3/. The simulations were carried out at a gate-source voltage of -1V and a drain-source voltage of 15V. Under similar conditions, the output resistance decreases from 1.2/spl times/10/sup 6/ /spl Omega///spl mu/m to 1.0/spl times/10/sup 5/ /spl Omega///spl mu/m, and the transconductance decreases from 5.9mS//spl mu/m to 5.3mS//spl mu/m, and f/sub T/ decreases from 11GHz to 8GHz.