Placement for modern FPGAs

Modern FPGAs are not only increasing in size but have also become more complex with many new features not found in the previous FPGA generation. This demands more powerful physical design automation tools and better solutions for both old and new problems. In this paper, we describe a novel net-based force-directed FPGA placement algorithm. It outperforms the state-of-the-art FPGA performance-driven placement tool, VPR by A. Marquardt et al. [2000], with 10.7% shorter critical path delay and 11.5% shorter total wire length after routing over a set of MCNC benchmarks. In addition, we describe the new constrained I/O placement problem in modern FPGAs and present a powerful integer linear programming based approach to solve it. We applied our proposed method on a large set of benchmarks to show that the existing solution method implemented in Altera's Quartus II tool suite is far from optimal.