A spread-spectrum clock generator using a capacitor multiplication technique

This paper presents a capacitor multiplication technique to reduce the required capacitance in the loop filter for a spread spectrum clock generator (SSCG). It has been fabricated to verify the proposed technique in a 0.35/spl mu/m single-poly quadruple-metal CMOS process. Based on the proposed capacitor multiplication technique, an SSCG with the spread ratios of 0.375%, 0.75%, 1.125% and 1.5% is also presented.