Synthesis method for switched-capacitor FIR decimators and interpolators

A method is given for the systematic synthesis of FIR (finite-impulse-response) switched-capacitor decimation and interpolation filters that includes the derivation of an optimum clocking scheme. The latter allows the maximum possible settling times for the operational amplifiers (OAs), thus minimizing response errors associated with finite OA slew-rate and bandwidth. An example, in which the time allowed for OA settling in a published circuit is increased by considerable factors, is given.<>