A VLSI design of new memory reduction turbo code decoder

In this paper we present the VSLI implementation of memory-reduced turbo decoder. According to the scheduling analysis, the backward recursion can be reversed in order to be directly operated on with forward recursion. The comparison result shows it can effectively reduce the memory size up to half size of the previous works. A core area 3.04 /spl times/ 3.04 mm/sup 2/, clock frequency 145 MHz in UMC 0.18/spl mu/m Ip6m CMOS process prototyping chip is implemented to verify our memory-reduced approach. For 3GPP standard, the proposed decoder can obtain 12Mb/s decoding rate when operating at 145 MHz with 6 iterations.