Algorithm for the automatic verification of complex mixed-signal ICs regarding ESD-stress

In this publication, an algorithm is described which automates the verification of a complex integrated circuit (IC) with regard to the behaviour under transient high current impulses (e.g. ESD). In order to reduce the complexity of the circuit for a later transient simulation with high current simulation models, the electric state of the circuit under stress is analysed in a simplified way enabling the efficient automated analysis of the total IC. A manual extraction of the relevant circuit parts for such a transient analysis can thus be avoided. The algorithm is embedded in a commercial design framework for IC-design and uses the data structures already existing.