A low-power 22-bit incremental ADC with 4 ppm INL, 2 ppm gain error and 2 /spl mu/V DC offset

A low power 22bit incremental ADC, including an on-chip digital filter and a low noise/low drift oscillator, was realized in a 0.6-/spl mu/m CMOS process. It incorporates a novel offset cancellation scheme based on fractal sequences, a novel high accuracy gain control circuit, and a novel reduced complexity realization for the on chip sine filter. The measured output noise was 0.28 ppm (2.8 /spl mu/V/sub RMS/), the dc offset 2 /spl mu/V, the gain error 2 ppm, and the INL 4 ppm. The chip operates with a single 2.7-5 V supply, and draws only 125 /spl mu/A current during conversion.