An accurate and efficient multiple delay simulator for MOS logic circuits using polynomial approximation

A technique is proposed for the multiple delay simulation of NMOS and CMOS logic circuits. For the simple inverter the rise or fall delay time is approximated by a product of polynomials of the input waveform slope, the output loading capacitance, and the device configuration ratio, with the polynomial coefficients so determined as to best fit the SPICE simulation results for a given fabrication process. This approach can easily be extended to the case of multiple input transitions. The simulation results show that the proposed method can predict the delay times within 5% error and with a speedup of a factor of three orders of magnitude for several circuits tested, as compared with the SPICE simulation.<>