Turbo codes - digital IC design

This paper presents a digital ASIC implementation of turbo encoder and simulation of the encoder and the decoder. The simulations determine the impact of decoder iterations, encoder transfer function and block size on latency, throughput and bit error rate. The paper proposes a design of turbo encoding hardware with dual-port on-chip memory targeting 0.18 /spl mu/m CMOS technology that reduces the memory requirements to half architectural and block level consideration are made to reduce power and area requirements while achieving a latency of "packet size + 5" clock cycles. Estimated power and area are 54.19mW and 12.0 mm/sup 2/ respectively.