Design of 12-bit 100-MHz current-steering DAC for SOC applications

In this paper, we propose a 12-bit 100-MHz current-steering digital-to-analog converter (DAC) for system-on-a-chip (SOC) applications. We adapt the segmented architecture to design this DAC to obtain better performances of INL, glitch energy, and monotonicity. The segmented architecture includes 7-MSBs which are decoded into 127 equally weighted current sources and 5-LSBs which are corresponding to binary-weighted current sources. Based on the TSMC 0.35/spl mu/m 2p4m CMOS technology, we use HSPICE to simulate the proposed DAC. The simulation results show that the proposed DAC has the following characteristics: INL < /spl plusmn/0.4LSB, DNL < /spl plusmn/0.25LSB, and settling time less than 9ns. The proposed converter's spurious free dynamic ranges (SFDRs) for are larger than 80 dB and 65 dB at an update rate (f/sub CLK/) 100MHz and its output frequencies are 1 MHz and 49 MHz, respectively. The power consumption is 47 mW at the maximum conversion rate.