An area and power efficient discrete-time chaos generator circuit

A discrete-time chaos generator circuit suitable for low power applications is presented in this paper. The generator is based on a three-transistor circuit which creates an easily adjustable chaos map characteristic. The circuit has a very compact implementation which makes it suitable for applications where many random noise generators are required on the same chip. The operation of the circuit has been verified via simulations in a 0.6/spl mu/m CMOS process.