Chip scale topography evolution model for CMP process optimization

A new chip scale model integrating pad height distribution and it's interaction with topography on a patterned wafer was tested. Pad asperity height distribution was used to calculate mean contact pressure at a single asperity contact region. Material removal by a single asperity was evaluated from Hertzian elastic contact model and abrasive indentation model. Simulation on a test pattern predicted relatively higher removal rate and lower planarization efficiency with higher nominal down pressure. Oxide thickness variation over a test chip for a time period measured from specially designed test structure matched well with the model prediction.