Asynchronous network node design for network-on-chip

A network node for Proteo network-on-chip (NoC) has been developed in order to support globally-asynchronous locally-synchronous (GALS) communication in an on-chip system. The network node presented in this paper was implemented as a synthesizable intellectual property (IP) block in register-transfer level (RTL) using VHDL. The proposed design applies both asynchronous and synchronous circuits to make the globally asynchronous data transfer rate between network nodes independent of local clocks.