Flow mapping in the load balancing parallel packet switches

Our work is motivated by the desire to design a switching fabric with very large aggregate capacity. In this paper, we consider a parallel switching architecture consisting of multiple planes, with each plane working independently. Different from previous research into parallel packet switches, this new architecture tries to perform load balancing at the variable-length packet level. Furthermore, to guarantee the performance of end-to-end flow and to provide differentiated QoS using a traffic manager which works slower than the line rate, we designed a packet load balancing algorithm in the flow mapping manner. We show that such a flow mapping is practical, and can be implemented using state-of-the-art commercial SRAM.