Design and verification of a digital adaptive equalizer ASIC

The author describes the design and verification of a VLSI circuit which can be used to build up a complex-valued equalizer for digital radio modems operating at a symbol rate of typically 23.5 Mbd. Fabricated in a 2- mu m CMOS technology, the chip contains about 108000 transistors on a silicon area of 95 mm/sup 2/ and operates at a clock frequency of at least 23.5 MHz. The basic idea behind tackling the design complexity is to use regular, parameterizable, and optimized semisystolic macros as building blocks. It is shown that the applied design style allows a high level of design certainty and can ease the verification.<>