Effect of low-k dielectric material on 63nm MLC (multi-level cell) NAND flash cell arrays

We investigate the effect of applying oxide spacer into MLC NAND flash memory with 63nm design rule. The oxide spacer is effective on reducing cell to cell coupling with its low-k dielectric constant. The uniform cell V/sub th/ distribution of 0.6V fulfilling the MLC operation is obtained while maintaining fast programming speed and sufficient cell current.