Design procedure for two-stage CMOS opamp with flexible noise-power balancing scheme | IEEE Journals & Magazine | IEEE Xplore

Design procedure for two-stage CMOS opamp with flexible noise-power balancing scheme


Abstract:

This paper presents a basic two-stage CMOS opamp design procedure that provides the circuit designer with a means to strike a balance between two important characteristic...Show More

Abstract:

This paper presents a basic two-stage CMOS opamp design procedure that provides the circuit designer with a means to strike a balance between two important characteristics in electronic circuit design, namely noise performance and power consumption. It is shown in this paper that, unlike the previously reported design procedures, the proposed design step allows opamp designers to trade between noise performance and power consumption with greater flexibility. In order to verify the viability of the proposed design step, SPICE simulation results of the opamp designed by the proposed procedure, under a variety of temperature and process conditions, are given.
Page(s): 1508 - 1514
Date of Publication: 31 August 2005

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