Design of fixed-point multimedia hardware accelerator in specific SoC based on statistical analysis

Many communication, voice and image applications require dedicated hardware accelerator to achieve acceptable levels of performance and cost in SoC (system-on-chip). This is particularly true of real-time applications that have strict timeline requirement on processing throughput and latency. This paper proposes a novel method for designing fixed-point multimedia hardware accelerator and outlines a good architecture for real-time low cost SoC designs with a generic RISC (reduced instruction set computer) processor core and extra multimedia hardware accelerator (MMA) needed in order to implement high computational cost multimedia calculations without a digital signal processor. In any case, the proposed architecture has a very good result for real-time low cost devices, which is the biggest request in the market today.