Block-decoded sense-amplifier driver for high-speed sensing in DRAM's

Safe sensing of the weak cell signal in DRAMs with low sense signals and fast sensing with low peak currents, both important design demands in 64- and 256-Mb DRAM development, are addressed. A block-decoded sense-amplifier driver concept is proposed. Optimized trigger pulse shapes are formed with local driver circuits to achieve high sensing safety at the beginning of the sensing period as well as fast amplification in the cell block containing the addressed memory cell. The nonaddressed blocks are triggered more slowly to reduce the peak current. Thus, reliable sensing of small initial sense signals is obtained in the shortest possible time, while the total current is kept small. As an example, for a 16-Mb DRAM, the sensing time-and hence the access time-can be reduced by at least 5 ns and is about 50% of the conventional sensing time.<>