Session 28 overview - clocking and I/O

Low jitter and low power are competing demands on the clock networks of systems running at GHz speeds. In addition, testability concerns require that low jitter be verified accurately, quickly, and at low cost. The papers in the first half of this session address high-speed clock generation, distribution, and testing. The second half of the session looks at three multi-Gb/s/pin I/O interfaces, and an innovative approach to interfacing today's deep-submicron chips with high-voltage legacy systems.