A 4/sup th/-order 86dB CT /spl Delta//spl Sigma/ ADC with two amplifiers in 90nm CMOS

A fourth-order 1b CT /spl Delta//spl Sigma/ converter using a two-amplifier loop and a 267MHz sampling frequency is implemented in 90nm CMOS. A double-loop architecture couples passive poles with a reduced number of active blocks to improve area and power while achieving 86dB peak SNR over a 600kHz band.